Patent attributes
A network device includes a packet processor, a plurality of interface circuits, a phase-locked loop (PLL) circuit and a configuration controller. The interface circuits are configured to transmit and receive signals to/from other devices that are coupled to the network device. A master interface circuit among the interface circuits is configured to recover a network clock from a received signal. The PLL circuit is configured to generate an interface clock based on a system clock of the network device and a configuration of the PLL circuit and to provide the interface clock to the plurality of interface circuits to govern communication timings of the interface circuits. The configuration controller is configured to detect a difference of the interface clock relative to the recovered network clock, and to determine the configuration of the PLL circuit based on the difference to govern operation of the PLL circuit.
