US Patent 10209998 Multi-threading processor and a scheduling method thereof

A processor includes an execution unit, a retirement module, a first retirement counter, a second retirement counter, and an adjustment module. The execution unit executes instructions of a first thread and a second thread by simultaneous multithreading. The retirement module retires the executed instructions of the first thread in order of the first-thread instruction sequence, and retires the executed instructions of the second thread in order of the second-thread instruction sequence. The first retirement counter determines a first multi-thread retirement rate of the first thread. The second retirement counter determines a second multi-thread retirement rate of the second thread. The adjustment module adjusts the proportions of hardware resources respectively occupied by the first thread and the second thread according to the first multi-thread retirement rate and the second multi-thread retirement rate, so that the processor executes at its most efficient level of performance.