Patent attributes
A shared memory computing device optimised for executing realtime software that has at least one interconnect master, a shared memory, N cache modules and M processor cores, where the value of N>=1 and M =N. Each of the N cache modules has a means to implement an update-type cache coherency policy across those N cache modules. Each processor core is assigned a different one of the N cache modules as that processor core's private cache. Furthermore, the memory transfer request latency of non-atomic memory transfer requests issued by each of the M processor cores to the shared memory is not modified by: (a) the memory transfer requests issued by any of the other M processor cores; or (b) the memory transfer requests issued by at least one other interconnect master.
