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US Patent 10212260 SerDes architecture with a hidden backchannel protocol

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Patent
Patent

Patent attributes

Patent Jurisdiction
United States Patent and Trademark Office
United States Patent and Trademark Office
Patent Number
10212260
Date of Patent
February 19, 2019
Patent Application Number
15654446
Date Filed
July 19, 2017
Patent Citations Received
‌
US Patent 11451417 Power-efficient nonlinear equalizers and methods
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US Patent 11349704 Physical layer interface with redundant data paths
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US Patent 11424968 Retimer training during link speed negotiation and link training
‌
US Patent 11451262 Spread spectrum clock converter
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US Patent 11032111 Serdes pre-equalizer having adaptable preset coefficient registers
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US Patent 11032103 Ethernet link extension method and device
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US Patent 11646959 Active ethernet cable with broadcasting and multiplexing for data path redundancy
0
Patent Primary Examiner
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David S Huang
Patent abstract

An illustrative multi-lane communication method implements a hidden backchannel to communicate equalization information and/or other link-related data without impinging on the user bandwidth allocated by the relevant articles of IEEE Std 802.3. One embodiment is implemented by a transceiver: (a) receiving signals from different receive channels; (b) converting each receive channel signal into a lane of a multi-lane receive data stream via demodulation and error measurement; (c) deriving outgoing backchannel information based at least in part on the error measurement; (d) detecting alignment markers in each lane of the multi-lane receive data stream; (e) extracting incoming backchannel information from a backchannel field following each alignment marker in at least one lane of the multi-lane receive data stream; and (f) modifying the multi-lane receive data stream to obtain a modified multi-lane receive data stream by replacing backchannel fields with PCS (Physical Coding Sublayer) alignment markers, thereby creating sets of grouped PCS alignment markers in said at least one lane.

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