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US Patent 10217667 3D semiconductor device, fabrication method and system

OverviewStructured DataIssuesContributorsActivity
Is a
Patent
Patent
Date Filed
February 24, 2018
Date of Patent
February 26, 2019
Patent Application Number
15904347
Patent Citations Received
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US Patent 12105650 Quasi-volatile system-level memory
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US Patent 11508445 Capacitive-coupled non-volatile thin-film transistor strings in three dimensional arrays
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US Patent 12073082 High capacity memory circuit with low effective latency
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US Patent 12096630 Staircase structures for electrically connecting multiple horizontal conductive layers of a 3-dimensional memory device
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US Patent 11488676 Implementing logic function and generating analog signals using NOR memory strings
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US Patent 10833103 Semiconductor memory device
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US Patent 11610914 Vertical thin-film transistor and application as bit-line connector for 3-dimensional memory arrays
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US Patent 11665908 Semiconductor memory device incorporating hafnium oxide insulative portions
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US Patent 11675500 High capacity memory circuit with low effective latency
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US Patent 11749344 Three-dimensional vertical nor flash thin-film transistor strings
•••
Patent Jurisdiction
United States Patent and Trademark Office
United States Patent and Trademark Office
Patent Number
10217667
Patent Primary Examiner
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Walter H Swanson

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