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US Patent 10217728 Semiconductor package and semiconductor process
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Patent
Date Filed
November 22, 2016
Date of Patent
February 26, 2019
Patent Application Number
15359403
Patent Citations Received
US Patent 11942385 Semiconductor package structure
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US Patent 10777536 Semiconductor package with air cavity
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US Patent 11569196 Chip to chip interconnect in encapsulant of molded semiconductor package
US Patent 10916524 Stacked dice systems
US Patent 11587800 Semiconductor package with lead tip inspection feature
US Patent 11289436 Semiconductor package having a laser-activatable mold compound
US Patent 11296000 Formation of conductive connection tracks in package mold body using electroless plating
Patent Inventor Names
You-Lung Yen
0
Bernd Karl Appelt
0
Kay Stefan Essig
0
Patent Jurisdiction
United States Patent and Trademark Office
Patent Number
10217728
Patent Primary Examiner
S. V. Clark
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