US Patent 10223001 Memory system
Patent 10223001 was granted and assigned to Toshiba Memory Corporation on March, 2019 by the United States Patent and Trademark Office.
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When receiving a write command from a host, a memory system according to one embodiment updates first correspondence information indicating the correspondence relationship between a logical address corresponding to user data and a position in a first memory and transmits the user data which has been stored in a second memory to the first memory. When the transmission is completed, the memory system writes the user data to the first memory. When the update and the transmission are completed, the memory system releases a memory area which stores the user data such that the memory area can be used as a memory area for other data.
US Patent 10223001 Memory system
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