Patent 10236044 was granted and assigned to Toshiba Memory Corporation on March, 2019 by the United States Patent and Trademark Office.
A memory system includes a semiconductor memory and a controller. The controller is configured to perform a read operation on the semiconductor memory in response to a read instruction received from a host. In response to the read instruction that includes a first logical address, the controller converts the first logical address into a first physical address, and issues a read command and a second physical address different from the first physical address, to the semiconductor memory.