US Patent 10241959 Coding wave-pipelined circuits with buffering function in HDL

The present invention teaches how to code a new or existing circuit of wave-pipelining with a buffering function in HDL (Hardware Description Language). The circuit comprises at least one critical path component (CPC) and a wave-pipelined component (WPC). A WPC comprises one Data_position_shifter per CPC, an Input_register_rotator if the circuit has multiple input registers, a Combinational_logic_rotator if the circuit has multiple pieces of combinational logic and a sole output register, a buffering controller and up to three FIFOs. All critical paths provide a first storage, FIFO_1 provides a second storage for output-ready data; FIFO_2 is to store indexes of output registers if the circuit has multiple output registers; FIFO_3 is to store assistant data. Each output register has an attached output register state machine which has three states: idle state, active state and buffered state. A locked piece of combinational logic is blocked from latching onto its connected or shared output register to avoid data contamination.