US Patent 10242419 Compiler optimization to reduce the control flow divergence

In one embodiment a graphics processing system comprises a graphics processor having execution logic and shared memory and a shader compiler unit to compile a shader program for execution by the execution logic of the graphic processor, wherein the shader is to optimize the shader program during the compile, wherein to optimize the shader program includes to convert a divergent block of parallel instructions into a divergent block and a non-divergent block of instructions.