Patent attributes
An array of resistance cells has a number M of rows and a number N of columns of resistance cells. Each cell comprises a transistor having a threshold, representing a weight factor Wnm of the cell, and a resistive element in series with the transistor. Each cell has a cell resistance having a first value when the transistor is on and a second value when the transistor is off. A set of source lines is coupled to the resistance cells in respective columns. A set of bit lines is coupled to the resistance cells in respective rows, signals on the bit lines representing inputs x(m) to the respective rows. A set of word lines is coupled to gates of the transistors in the resistance cells in respective columns. Current sensed at a particular source line represents a sum of products of the inputs x(m) by respective weight factors Wnm.
