US Patent 10243882 Network on chip switch interconnect

A disclosed network on chip includes a semiconductor die and switches disposed on the semiconductor die. Each switch has ports configured to receive packets from and transmit packets to at least two other switches. Each switch includes first circuitry that specifies a first mapping of interface identifiers of interfaces on the semiconductor die to port identifiers, and second circuitry that specifies a second mapping of region identifiers of regions of the semiconductor die to port identifiers. Each switch further includes third circuitry coupled to the first and second circuitry. The third circuitry is configured to select, in response to an input packet that specifies a destination region and a destination interface, a port based on the specification of the destination region, specification of the destination interface, first mapping, and second mapping, and output the packet on the selected port.