US Patent 10249731 Vertical FET with sharp junctions

VFET devices and techniques for formation thereof having well-defined, sharp source/drain-to-channel junctions are provided. In one aspect, a method of forming a VFET device includes: forming a SiGe layer on a substrate, wherein the SiGe layer as formed on the substrate is undoped; forming an Si layer on the SiGe layer, wherein the Si layer as formed on the SiGe layer is undoped; patterning fins in the Si layer; forming sacrificial spacers along sidewalls of the fins; forming recesses in the SiGe layer between the fins; growing an epitaxial material in the recesses, wherein the epitaxial material grown in the recesses includes a source and drain dopant; annealing the epitaxial material to diffuse the source drain dopant into the SiGe layer under the fins forming bottom source and drains of the VFET device; and removing the sacrificial spacers. A VFET device formed by the method is also provided.