US Patent 10255834 Parallel redundant chiplet system for controlling display pixels

A parallel redundant integrated-circuit system includes an input connection, an output connection and first and second active circuits. The first active circuit includes one or more first integrated circuits and has an input connected to the input connection and an output connected to the output connection. The second active circuit includes one or more second integrated circuits and is redundant to the first active circuit, has an input connected to the input connection, and has an output connected to the output connection. The second integrated circuits are separate and distinct from the first integrated circuits.