US Patent 10255972 Memory system and control method of memory system

A memory system includes a non-volatile memory and a controller configured to perform a read re-try in response to a failed normal read. The read re-try includes a first read of data at a first read voltage, a second read of data at a second read voltage obtained by shifting the first read voltage by a first shift amount, which is determined according to a bit count value obtained by counting a number of predetermined bit values in the first read, a third read of data carried out a plurality of times at a plurality of third read voltages, wherein each of the plurality of third read voltages are shifted from each other by a second shift amount, and a final read of data at a read voltage that is set closer to the second read voltage than the first read voltage.