Patent attributes
A method for timing recovery for a high-speed data transmission system may be provided. The method comprises receiving an analog input signal at an ADC and passing processed digital signal samples to a Viterbi detector. The method also comprises receiving at least one processed signal sample and at least two sets of at least one candidate symbol each from the Viterbi detector and/or the processed signal samples by timing error detectors and forwarding output digital signals of the timing error detectors via loop filters to related multiplexers. Furthermore, the method comprises selecting one digital signal from each of the multiplexers using a select signal generated by the Viterbi detector, and deriving a control signal controlling a sampling clock of the analog-to-digital converter by at least one of the selected digital signals from the multiplexers.
