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US Patent 10263919 Buffer assignment balancing in a network device

Patent 10263919 was granted and assigned to Innovium on April, 2019 by the United States Patent and Trademark Office.

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Is a
Patent
Patent
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Patent attributes

Patent Applicant
Innovium
Innovium
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Current Assignee
Innovium
Innovium
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Patent Jurisdiction
United States Patent and Trademark Office
United States Patent and Trademark Office
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Patent Number
102639190
Patent Inventor Names
Ajit Kumar Jain0
Puneet Agarwal0
William Brad Matthews0
Bruce Hui Kwan0
Date of Patent
April 16, 2019
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Patent Application Number
158047790
Date Filed
November 6, 2017
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Patent Citations Received
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US Patent 12095673 System and method for latency critical quality of service using continuous bandwidth control
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US Patent 10735221 Flexible processor of a port extender device
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US Patent 11249916 Single producer single consumer buffering in database systems
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US Patent 11290389 System and method for latency critical quality of service using continuous bandwidth control
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US Patent 11709835 Re-ordered processing of read requests
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US Patent 11343358 Flexible header alteration in network devices
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US Patent 11924111 Signal transfer device and signal transfer method
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US Patent 11977548 Allocating partitions for executing operations of a query
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Patent Primary Examiner
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Kouroush Mohebbi
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Patent abstract

Techniques for more optimally balancing operations across a set of buffers, such as in buffering packets in a network device or in other contexts, are disclosed. The techniques make use of an ordered list of buffers from which the next available buffer is selected for each operation, as needed. The buffers are first prioritized based on the state(s) of the relevant buffers and/or other factors. The resulting ordered list is then processed using re-ordering logic. This re-ordering logic may, for example, randomly or pseudo-randomly trade the positions of various sets of buffers within the prioritized list. Among other effects, the re-ordering logic thus reduces buffer skew problems from delayed propagation of buffer state information and other issues. In an embodiment, the re-ordering logic is divided into multiple levels of processing, with each level separately passing through the list. Each level of processing may utilize differently configured re-ordering logic.

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