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US Patent 10269429 Architecture for 3-D NAND memory

Patent 10269429 was granted and assigned to Micron Technology on April, 2019 by the United States Patent and Trademark Office.

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US Patent 11862238 Multi-deck memory device including buffer circuitry under array
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Patent abstract

Apparatuses are described that include stacked arrays of memory cell strings and their methods of operation. Apparatuses include architectures that reduce the use of several common components, allowing greater device density and smaller device size for a given semiconductor area.

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https://pdfpiw.uspto.gov/.piw?Docid=1026942900
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US Patent 11653497 Semiconductor apparatus with multiple tiers, and methods
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US Patent 10510414 3D NAND memory Z-decoder
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US Patent 11450381 Multi-deck memory device including buffer circuitry under array
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US Patent 11380397 Architecture for 3-D NAND memory
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US Patent 10978155 3D NAND memory Z-decoder
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US Patent 10803944 Architecture for 3-D NAND memory
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US Patent 10510414 3D NAND memory Z-decoder
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 US Patent 10269429 Architecture for 3-D NAND memory

Infobox
Is a
Patent
Patent
Patent applicant
Micron Technology
Micron Technology
Current assignee
Micron Technology
Micron Technology
Patent jurisdiction
United States Patent and Trademark Office
United States Patent and Trademark Office
Patent number
10269429
Date of patent
April 23, 2019
Patent application number
14626540
Date Filed
February 19, 2015
Patent citations
‌
US Patent 10074431 3D NAND memory Z-decoder
Patent primary examiner
‌
Min Huang

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