Patent attributes
A memory device according to an embodiment includes word lines stacked in a third direction perpendicular to a first direction and a second direction; main bit lines including a first main bit line and extending in the second direction; transistors including first and second transistors of which the channel width is greater than the width of the main bit lines; sub-bit lines extending in the third direction and including a first sub-bit line electrically connected to the first main bit line, with the first transistor interposed therebetween, and a second sub-bit line electrically connected to the first main bit line, with the second transistor interposed therebetween, and being adjacent to the first sub-bit line, a line segment virtually connecting the first sub-bit line and the second sub-bit line intersecting the second direction; and a resistance-change layer provided between the word lines and the sub-bit lines.