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US Patent 10269586 Package structure and methods of forming same

OverviewStructured DataIssuesContributorsActivity
Is a
Patent
Patent
Date Filed
February 13, 2015
Date of Patent
April 23, 2019
Patent Application Number
14621567
Patent Citations Received
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US Patent 11935856 Semiconductor device having a redistribution layer
0
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US Patent 11790219 Three dimensional circuit implementing machine trained network
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US Patent 11824006 Semiconductor package
0
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US Patent 11881454 Stacked IC structure with orthogonal interconnect layers
0
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US Patent 10580735 Stacked IC structure with system level wiring on multiple sides of the IC die
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US Patent 10580757 Face-to-face mounted IC dies with orthogonal top interconnect layers
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US Patent 10586786 3D chip sharing clock interconnect layer
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US Patent 10593667 3D chip with shielded clock lines
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US Patent 10600735 3D chip sharing data bus
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US Patent 10600691 3D chip sharing power interconnect layer
•••
Patent Jurisdiction
United States Patent and Trademark Office
United States Patent and Trademark Office
Patent Number
10269586
Patent Primary Examiner
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Matthew L Reames

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