Patent attributes
An inverter circuit includes: a first P-channel MISFET having a source connected to a positive-side terminal and a drain connected to an output terminal; a first N-channel MISFET having a source connected to a negative-side terminal and a drain connected to the output terminal; a first delay element connected between a gate of the first P-channel MISFET and an input terminal to which an input signal is supplied; first switch element connected in parallel with the first delay element between the input terminal and the gate of the first P-channel MISFET; a second delay element connected between the input terminal and a gate of the first N-channel MISFET; and a second switch element connected in parallel with the second delay circuit between the input terminal and the gate of the first N-channel MISFET. The first and second switch elements operate in response to a potential on the output terminal.