Patent attributes
A phase adjusting device provided includes a main delay circuit, a first converter, a second converter, a first buck circuit, and a second buck circuit. The main delay circuit receives an input clock signal to generate a main delay signal. The first converter receives the input clock signal to generate a first conversion signal. The second converter is coupled to the main delay circuit to receive the main delay signal and generate a second conversion signal. The first buck circuit is coupled to the first converter to receive the first conversion signal and generate a first buck voltage. The second buck circuit is coupled to the second converter to receive the second conversion signal and generate a second buck voltage. A first phase difference is formed between the main delay signal and the input clock signal.
