Structures for a passive device of an integrated circuits and associated fabrication methods. A semiconductor substrate having raised fins and an dielectric isolation layer between the fins is formed. An etch stop layer is formed over the dielectric isolation layer between fins of a passive device. An interlayer dielectric layer is formed over the fins and etch stop layer. The interlayer dielectric layer is selectively etched to form an opening for conductive contact to the fins, where the etch stop layer prevents etching of the dielectric isolation layer. A conductive contact is formed to contact the plurality of fins, with the conductive contact terminating at the etch stop layer.