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US Patent 10289604 Memory processing core architecture

Patent 10289604 was granted and assigned to Wisconsin Alumni Research Foundation on May, 2019 by the United States Patent and Trademark Office.

OverviewStructured DataIssuesContributorsActivity
Is a
Patent
Patent
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Current Assignee
Wisconsin Alumni Research Foundation
Wisconsin Alumni Research Foundation
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Date Filed
August 7, 2014
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Date of Patent
May 14, 2019
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Patent Applicant
Wisconsin Alumni Research Foundation
Wisconsin Alumni Research Foundation
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Patent Application Number
14453990
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Patent Citations Received
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US Patent 11790219 Three dimensional circuit implementing machine trained network
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US Patent 10892252 Face-to-face mounted IC dies with orthogonal top interconnect layers
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US Patent 10950547 Stacked IC structure with system level wiring on multiple sides of the IC die
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US Patent 10970627 Time borrowing between layers of a three dimensional chip stack
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US Patent 10978348 3D chip sharing power interconnect layer
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US Patent 11599299 3D memory circuit
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US Patent 11289333 Direct-bonded native interconnects and active base die
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US Patent 11557516 3D chip with shared clock distribution network
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US Patent 10886177 3D chip with shared clock distribution network
Patent Inventor Names
Jaikrishnan Menon
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Karthikeyan Sankaralingam
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Lorenzo De Carli
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Patent Jurisdiction
United States Patent and Trademark Office
United States Patent and Trademark Office
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Patent Number
10289604
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Patent Primary Examiner
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S. Sough
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