US Patent 10319450 Semiconductor memory device

A semiconductor memory device includes a first memory cell which is capable of being set to any one of at least eight threshold voltages, a first bit line, a word line, and a sense amplifier which is connected to the first bit line. A verification operation for verifying the threshold voltage of the first memory cell is performed after a programming operation is performed on the first memory cell, and the verification operation includes seven verification operations. The sense amplifier applies a charging voltage to the first bit line during two of the seven verification operations, and does not apply the charging voltage to the first bit line during the remaining five of the seven verification operations.