US Patent 10320509 Fail safe clock buffer and clock generator

Techniques for generating a fail safe clock signal improves reliability of one or more output clock signals generated based on one or more input clock signals and an internally generated reference clock signal. By continuously monitoring the frequencies of the one or more input clock signals and reducing or eliminating effects of any static frequency offset between multiple input clock signals, the fail safe clock generator can detect very small relative frequency changes between the inputs or within a particular input. By comparing the input clock frequencies against a reference clock signal frequency over time of a clock signal generated by an internal oscillator, the fail safe clock generator may further detect which one of multiple input clocks has frequency deviation. The fail safe clock generator uses an internal oscillator generating a reference clock signal having a short-term stable frequency.