US Patent 10325006 Scalable architecture for analog matrix operations with resistive devices

In some aspects, a method for performing analog matrix inversion on a matrix with a network of resistive device arrays B, W, Q, and C is described. The method may include initializing arrays W, Q, B and C, updating the connections of array W in parallel and array Q in parallel until a predetermined condition is satisfied, and responsive to determining that the predetermined condition is satisfied, outputting an inverted matrix based on outputs from the connections of arrays B, W, Q, and C.