Patent attributes
A system including a processor; and a memory having stored thereon computer program code that, when executed by the processor, controls the processor to: receive data indicative of a plurality of sequence diagrams; for each of the plurality of sequence diagrams, generate a corresponding architecture diagram by: identifying a plurality of participants within the sequence diagram, transforming each of the plurality of participants into a plurality of nodes, identifying a plurality of messages identifying at least one message participant, and transforming the identified plurality of messages by establishing a single edge between respective nodes of the plurality of nodes corresponding to message participants identified by one or more messages of the plurality of messages; and merge the corresponding architecture diagrams of each of the plurality of sequence diagrams to generate a master architecture diagram.
