US Patent 10338446 Semiconductor device having low resistance source and drain regions

A semiconductor device has a top-gate structure resistant to creation of parasitic capacitance between a low-resistance region formed in a semiconductor layer and a gate electrode. A TFT (100) has a low-resistance region, a portion of which has a first length (L1) ranging from a first position (P1) corresponding to an end of a gate insulating film to a region below a gate electrode (40), and the first length is substantially equal to a second length (L2) ranging from the first position (P1) to a second position (P2) corresponding to an end of the gate electrode (40). Thus, the overlap between the gate electrode (40) and either a source region (20 s) or a drain region (20 d) can be reduced, resulting in diminished parasitic capacitance.