US Patent 10347283 Clock data recovery in multilane data receiver

Methods and systems are described for obtaining, at a phase-error aggregator, a plurality of data-derived phase-error signals for two or more data lanes of a multi-wire bus, each data-derived phase-error signal generated using at least (i) a phase of one or more phases of a local oscillator signal and (ii) a corresponding data signal associated with one of the two or more data lanes, generating a composite phase-error signal representing a combination of the two or more obtained data-derived phase-error signals, receiving the composite phase-error signal at a loop filter responsively generating an oscillator control signal, and receiving the oscillator control signal at a local oscillator and responsively adjusting a timing of the local oscillator to adjust the one or more phases of the local oscillator signal.