US Patent 10347719 Nanosheet transistors on bulk material

A semiconductor structure. The structure includes first source/drain located in a first source/drain region. The structure includes a second source/drain located in a second source/drain region. The structure includes a plurality of semiconductor nanosheets located between the first source/drain and the second source/drain in a gate region. The structure includes an insulating layer separating the first source drain from a bulk substrate. The bulk substrate may have a first horizontal surface in the gate region, a second horizontal surface in the first source/drain region, and a connecting surface forming an at least partially vertical connection between the first horizontal surface and the second horizontal surface. The insulating layer may be directly on the second horizontal surface and the connecting surface.