US Patent 10355121 3D semiconductor device with stacked memory

A semiconductor device, the device including: a first stratum including memory periphery circuits; a second stratum including an array of first memory cells, where the first stratum is overlaid by the second stratum; a third stratum including an array of second memory cells, where the second stratum is overlaid by the third stratum, where the first memory cells include a plurality of first polysilicon structures and the second memory cells include a plurality of second polysilicon structures, and where at least one of the first memory cells is self-aligned to at least one of the second memory cells.