Patent attributes
A resistive random access memory stack is formed on a surface of a faceted drain-side structure that is present on one side of a functional gate structure. The functional gate structure and the faceted drain-side structure are located on a topmost surface of a fully depleted semiconductor channel material layer. In some embodiments, the resistive random access memory stack includes a bottom electrode, a resistive switching layer and a top electrode. In other embodiments, the resistive random access memory stack includes a resistive switching layer and a top electrode. In such an embodiment, a drain-side metal semiconductor alloy of the faceted drain-side structure is used as the bottom electrode of the resistive random access memory device.
