US Patent 10381288 Packaged semiconductor die and CTE-engineering die pair

Packaged semiconductor die and CTE-engineering die pairs and methods to form packaged semiconductor die and CTE-engineering die pairs are described. For example, a semiconductor package includes a substrate. A semiconductor die is embedded in the substrate and has a surface area. A CTE-engineering die is embedded in the substrate and coupled to the semiconductor die. The CTE-engineering die has a surface area the same and in alignment with the surface area of the semiconductor die.