US Patent 10387606 Validating a clock tree delay

A computer implemented method for validating a clock tree includes estimating a first number of a multitude of first buffers disposed in the clock tree path, and selecting a first scaling coefficient in accordance with the first number. The computer implemented method further includes scaling a first delay associated with the multitude of first buffers in accordance with the selected first scaling coefficient, and generating a second multitude of second buffers disposed in the clock tree path defined by a second number greater than the first number.