Patent attributes
A memory cell within an integrated-circuit memory component receives a first control signal that transitions between supply voltage levels of a first voltage domain and a second control signal that transitions between supply voltage levels of a second voltage domain different from the first voltage domain. In response to the transitions of the first and second control signal, output-enable circuitry within the memory cell transitions an output-enable signal between one of the supply voltage levels of the first voltage domain and one of the supply voltage levels of the second voltage domain to enable output signal generation on an output signal line coupled to the memory cell.