US Patent 10395988 Vertical FET transistor with reduced source/drain contact resistance

A method is presented for reducing contact resistance and parasitic capacitance. The method includes forming a plurality of fins over a semiconductor substrate, forming a bottom source/drain region between the plurality of fins, forming a bottom spacer over the bottom source/drain region, forming high-k metal gates over the bottom spacers, and forming a top spacer over the high-k metal gates. The method further includes forming an interlayer dielectric (ILD) over the top spacer, recessing the ILD to expose top sections of the plurality of fins, depositing an epitaxial material over each of the top sections of the plurality of fins, forming a dielectric film over the epitaxial material such that air-gaps are created between the top sections of the plurality of fins and recessing the dielectric film to expose top sections of the epitaxial material and to deposit a silicide metal liner and a conductive material thereon.