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US Patent 10402365 Data lane validation procedure for multilane protocols
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Date Filed
November 27, 2018
Date of Patent
September 3, 2019
Patent Application Number
16201369
Patent Citations
US Patent 10139875 Farewell reset and restart method for coexistence of legacy and next generation devices over a shared multi-mode bus
US Patent 10153873 Physical layer protocol data unit format applied with space time block coding in a high efficiency wireless LAN
US Patent 10146733 High performance interconnect physical layer
US Patent 10241955 Dynamically adjustable multi-line bus shared by multi-protocol devices
US Patent 10007628 Dynamically adjustable multi-line bus shared by multi-protocol devices
US Patent 10073808 Multichip package link
Patent Jurisdiction
United States Patent and Trademark Office
Patent Number
10402365
Patent Primary Examiner
Steven G Snyder
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