US Patent 10402534 Integrated circuit layout methods, structures, and systems

A method of generating a layout of an IC includes identifying a target pin in a first cell in an IC layout, the first cell being adjacent to a second cell and sharing a boundary with the second cell, and determining whether or not the target pin is capable of being extended into the second cell. Based on a determination that the target pin is capable of being extended into the second cell, the target pin is modified to include an extension into the second cell, the target pin thereby crossing the shared boundary. At least one of the identifying, determining, or modifying is executed by a processor of a computer.