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US Patent 10403631 Three-dimensional ferroelectric memory devices
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Patent
Date Filed
August 13, 2018
Date of Patent
September 3, 2019
Patent Application Number
16102667
Patent Citations
US Patent 10153018 Ferroelectric memory cells
US Patent 10049720 Dynamic random access memory (DRAM)
0
Patent Citations Received
US Patent 12108603 Methods for forming on-chip capacitor structures in semiconductor devices
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US Patent 11476262 Methods of forming an array of capacitors
US Patent 11916149 Doped polar layers and semiconductor device incorporating same
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US Patent 11925031 Arrays of capacitors and arrays of memory cells
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US Patent 11949018 Doped polar layers and semiconductor device incorporating same
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US Patent 11949017 Doped polar layers and semiconductor device incorporating same
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US Patent 11956968 Memory device
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US Patent 11469327 Doped polar layers and semiconductor device incorporating same
US Patent 10763099 Wafer flatness control using backside compensation structure
US Patent 11289509 Double-gated ferroelectric field-effect transistor
•••
Patent Inventor Names
Qian Tao
0
Yushi Hu
0
Zhenyu Lu
0
Patent Jurisdiction
United States Patent and Trademark Office
Patent Number
10403631
Patent Primary Examiner
Allison Bernstein
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