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US Patent 10403739 Method for fabricating semiconductor device

OverviewStructured DataIssuesContributorsActivity
Is a
Patent
Patent
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Date Filed
January 9, 2018
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Date of Patent
September 3, 2019
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Patent Application Number
15865531
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Patent Citations Received
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US Patent 12136671 Gate-all-around field-effect transistor having source side lateral end portion smaller than a thickness of channel portion and drain side lateral end portion
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US Patent 10600889 Nanosheet transistors with thin inner spacers and tight pitch gate
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US Patent 11239359 Fabricating a gate-all-around (GAA) field effect transistor having threshold voltage asymmetry by thinning source side lateral end portion of the nanosheet layer
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US Patent 11329143 Nanosheet transistors with thin inner spacers and tight pitch gate
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US Patent 11929425 Nanowire stack GAA device with inner spacer
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Patent Inventor Names
Ki Yeon Park
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Tea Won Kim
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Yong Suk Tak
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Patent Jurisdiction
United States Patent and Trademark Office
United States Patent and Trademark Office
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Patent Number
10403739
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Patent Primary Examiner
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Walter H Swanson
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