US Patent 10410931 Fabricating method of nanosheet transistor spacer including inner spacer

A fabricating method of a nanosheet transistor includes: forming a plurality of sacrificial layers and a plurality of channel layers on a substrate, wherein the sacrificial layers and the channel layers are alternately arranged; forming a plurality of gates on an uppermost channel layer, wherein the gates are spaced apart from each other; forming a mask on each of the gates; selectively etching the sacrificial layers between the gates, wherein the sacrificial layers between the gates are removed by the etching; depositing a spacer material along sidewalls of the gates and in areas from which the sacrificial layers have been removed; and etching the spacer material to form sidewall spacers along the sidewalls of the gates and inner spacers between the channel layers.