Patent 10411028 was granted and assigned to Toshiba Memory Corporation on September, 2019 by the United States Patent and Trademark Office.
According to one embodiment, the source layer includes a semiconductor layer including a dopant. The columnar portions are disposed in an area between the separation portions. The columnar portions extend in the stacking direction through the stacked body and through the semiconductor layer. The columnar portions include a plurality of semiconductor bodies including sidewall portions contacting the semiconductor layer. The dopant diffusion prevention film is provided inside the semiconductor layer and separated from the columnar portions in an area between the columnar portions. The dopant diffusion prevention film is not provided inside the semiconductor layer in an area between the separation portion and the columnar portions.