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US Patent 10417460 Low power analog vector-matrix multiplier

Patent 10417460 was granted and assigned to Areanna Inc. on September, 2019 by the United States Patent and Trademark Office.

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Patent attributes

Current Assignee

Patent Jurisdiction

United States Patent and Trademark Office

Patent Number

Date of Patent

September 17, 2019

Patent Application Number

16141817

Date Filed

September 25, 2018

Patent Citations Received

US Patent 12118331 Bias unit element with binary weighted charge transfer lines

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US Patent 11476866 Successive approximation register using switched unit elements

US Patent 12014152 Multiplier-accumulator unit element with binary weighted charge transfer capacitors

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US Patent 12026479 Differential unit element for multiply-accumulate operations on a shared charge transfer bus

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US Patent 11469770 Architecture for multiplier accumulator using unit elements for multiplication, bias, accumulation, and analog to digital conversion over a shared charge transfer bus

US Patent 11567730 Layout structure for shared analog bus in unit element multiplier

US Patent 11055062 Switched capacitor vector-matrix multiplier

US Patent 11687738 Chopper stabilized bias unit element with binary weighted charge transfer capacitors

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Patent Primary Examiner

Joseph J Lauture

Patent abstract

Methods and apparatuses enable a general-purpose low power analog vector-matrix multiplier. This Abstract is not intended to limit the scope of the claims.

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