Patent attributes
The disclosed technology relates generally to semiconductor devices and more particularly to three dimensional semiconductor memory devices, such as vertical three dimensional non-volatile memory devices. In one aspect, a method of fabricating a memory device comprises providing, on a substrate, an alternating stack of control gate layers and dielectric layers. The method additionally includes forming a memory block. comprising forming at least one memory hole through the alternating stack, where the at least one memory hole comprises on its sidewalls a stack of a programmable material, a channel material and a dielectric material, thereby forming at least one memory cell. The method additionally comprises removing a portion of the alternating stack to form at least one trench, where the at least one trench forms at least part of a boundary of the memory block. The method additionally comprises partially removing the control gate layers exposed at a sidewall of the at least one trench, thereby forming recesses in the control gate layers. The method further comprises filling the recesses with an electrically conductive material, thereby forming electrically conductive plugs. In another aspect, a device formed using the method is also provided.
