Patent attributes
A semiconductor package includes a first semiconductor package including a first substrate and a lower semiconductor chip mounted on the first substrate, a second semiconductor package stacked on the first semiconductor package and including a second substrate and an upper semiconductor chip mounted on the second substrate, and an interposer substrate interposed between the first semiconductor package and the second semiconductor package and having a recess recessed from a lower surface facing the lower semiconductor chip, wherein the interposer substrate includes a dummy wiring layer disposed to be adjacent to the recess, in a region overlapped with the lower semiconductor chip, and no electrical signal is applied to the dummy wiring layer.
