US Patent 10446562 One-time programmable bitcell with partially native select device

An OTP memory device includes a first and a second doped region of the same polarity in a semiconductor substrate. The second doped region has a higher doping concentration than the first doped region. A drain region and a source region of an opposite polarity are also in the semiconductor substrate. The drain region is positioned over the first, higher doped region, and the drain is positioned over the second, lower doped region. The select device above the semiconductor substrate can form a channel in a channel region of the semiconductor substrate between the source region and the drain region. One portion of the select device is positioned over the first, lower doped region, and another portion of the select device is positioned over the second, higher doped region. An anti-fuse device is positioned above the second doped region and in part above a portion of the source region.