US Patent 10452797 Fault insertion for system verification
Patent 10452797 was granted and assigned to Synopsys on October, 2019 by the United States Patent and Trademark Office.
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Patent abstract
A computer implemented method of modifying a compiled design of an electronic circuit is disclosed. The method includes accessing a stored compilation representing the design, and causing the computer to generate a modified version of the stored compilation in response to an indication of a change to a portion of the design.
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Patent Applicant
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Patent Jurisdiction
Patent Number
104527970
Date of Patent
October 22, 2019
0Patent Application Number
145303590
Date Filed
October 31, 2014
0Official Website
Patent Citations Received
Patent Primary Examiner
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Patent Citations Received
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Is a
Patent Applicant
Current Assignee
Patent Jurisdiction
Patent Number
104527970
Date of Patent
October 22, 2019
0Patent Application Number
145303590
Date Filed
October 31, 2014
0Official Website
Patent Citations Received
Patent Primary Examiner
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US Patent 10452797 Fault insertion for system verification
Infobox
Is a
Patent applicant
Current assignee
Patent jurisdiction
Patent number
10452797
Date of patent
October 22, 2019
Patent application number
14530359
Date Filed
October 31, 2014
Patent primary examiner
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