Patent attributes
A display device operating at high speed is provided. The display device includes a buffer amplifier including first and second transconductance amplifiers and a buffer and pixels arranged in a matrix of x rows and y columns (x and y are integers greater than or equal to 2) and configured to express gray levels. In the first step, the offset voltage of the buffer amplifier is corrected using the second transconductance amplifier. Then, in the second step, a first analog signal corresponding to gray levels expressed by the pixels in two rows or more and x rows or less is input to one of a non-inverting input terminal and an inverting input terminal of the first transconductance amplifier, and a second analog signal corresponding to the first analog signal is output from an output terminal of the buffer.
