Patent attributes
A radar architecture comprising a computing device having a DC subtraction module, programmed to average a first value of a first pixel from a first received SAR image and a second value of a second pixel from a second received SAR image, to produce an averaged value, and to subtract the averaged value from the first value, resulting in a first DC subtracted pixel value, and to subtract the averaged value from the second value, resulting in a second DC subtracted pixel value; a DFT processing module programmed to receive the first DC subtracted pixel value and the second DC subtracted pixel value and to output a first DFT output comprising a plurality Doppler bins; and a detector module programmed to determine if the output of the DFT represents the presence of a target, and to estimate range-rate via a lookup table.